Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.11861/7592
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dc.contributor.authorLau, Wai Shingen_US
dc.contributor.authorLee, Kin Hongen_US
dc.contributor.authorProf. LEUNG Kwong Saken_US
dc.date.accessioned2023-03-27T02:50:30Z-
dc.date.available2023-03-27T02:50:30Z-
dc.date.issued2006-
dc.identifier.citationGECCO 2006 - Genetic and Evolutionary Computation Conference, 2006, vol. 1, pp. 839 - 845en_US
dc.identifier.isbn1595931864-
dc.identifier.isbn978-159593186-3-
dc.identifier.urihttp://hdl.handle.net/20.500.11861/7592-
dc.description.abstractGenetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system integrating GPP and FlowMap, a Hybridized GPP based Logic Circuit Synthesizer (HGPPLCS) is developed. To show the effectiveness of the proposed HGPPLCS, six combinational logic circuit problems are used for evaluations. Each problem is run for 50 times. Experimental results show that both the lookup table counts and the propagation gate delays of the circuits collected are better than those obtained by conventional design or evolved by GPP alone. For example, in a 6-bit one counter experiment, we obtained combinational digital circuits with 8 four-input lookup tables in 2 gate level on average. It utilizes 2 lookup tables and 3 gate levels less than circuits evolved by GPP alone. Copyright 2006 ACM.en_US
dc.language.isoenen_US
dc.publisherAssociation for Computing Machinery (ACM)en_US
dc.relation.ispartofGECCO 2006 - Genetic and Evolutionary Computation Conferenceen_US
dc.titleA hybridized genetic parallel programming based logic circuit synthesizeren_US
dc.typeConference Paperen_US
dc.identifier.doi10.1145/1143997.1144145-
item.fulltextNo Fulltext-
crisitem.author.deptDepartment of Applied Data Science-
Appears in Collections:Applied Data Science - Publication
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