Please use this identifier to cite or link to this item:
http://hdl.handle.net/20.500.11861/7609
Title: | Multi-logic-Unit Processor: A combinational logic circuit evaluation engine for genetic parallel programming |
Authors: | Lau, Wai Shing Li, Gang Lee, Kin Hong Prof. LEUNG Kwong Sak Cheang, Sin Man |
Issue Date: | 2005 |
Publisher: | Springer Verlag |
Source: | Lecture Notes in Computer Science, 2005, vol. 3447, pp. 167 - 177 |
Journal: | Lecture Notes in Computer Science |
Abstract: | Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. GPP Logic Circuit Synthesizer (GPPLCS) is a combinational logic circuit learning system based on GPP. The GPPLCS comprises a Multi-Logic-Unit Processor (MLP) which is a hardware processor built on a Field Programmable Gate Array (FPGA). The MLP is designed to speed up the evaluation of genetic parallel programs that represent combinational logic circuits. Four combinational logic circuit problems are presented to show the performance of the hardware-assisted GPPLCS. Experimental results show that the hardware MLP speeds up evolutions over 10 times. For difficult problems such as the 6-bit priority selector and the 6-bit comparator, the speedup ratio can be up to 22. © Springer-Verlag Berlin Heidelberg 2005. |
Type: | Conference Paper |
URI: | http://hdl.handle.net/20.500.11861/7609 |
ISSN: | 03029743 |
DOI: | 10.1007/978-3-540-31989-4_15 |
Appears in Collections: | Applied Data Science - Publication |
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