Lau, Wai ShingWai ShingLauLee, Kin HongKin HongLeeProf. LEUNG Kwong Sak2023-03-272023-03-272006GECCO 2006 - Genetic and Evolutionary Computation Conference, 2006, vol. 1, pp. 839 - 8451595931864978-159593186-3http://hdl.handle.net/20.500.11861/7592Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system integrating GPP and FlowMap, a Hybridized GPP based Logic Circuit Synthesizer (HGPPLCS) is developed. To show the effectiveness of the proposed HGPPLCS, six combinational logic circuit problems are used for evaluations. Each problem is run for 50 times. Experimental results show that both the lookup table counts and the propagation gate delays of the circuits collected are better than those obtained by conventional design or evolved by GPP alone. For example, in a 6-bit one counter experiment, we obtained combinational digital circuits with 8 four-input lookup tables in 2 gate level on average. It utilizes 2 lookup tables and 3 gate levels less than circuits evolved by GPP alone. Copyright 2006 ACM.enField Programmable Gate ArrayTechnology MappingLookUp TableGenetic Parallel ProgrammingFlowMapA Hybridized Genetic Parallel Programming Logic Circuit SynthesizerConference Paper10.1145/1143997.1144145